1. Field of the Invention
The present invention relates to very high frequency phase locked loops (PLL) and, in particular, to a wave synthesizer that creates multiple-phase trapezoidal waveforms that drive the PLL's frequency controlled oscillator, resulting in a PLL with greatly improved response.
2. Discussion of the Related Art
Commonly-assigned U.S. Pat. No. 5,224,125, issued Jun. 29, 1993, discloses a signed phase-to-frequency (P-to-F) converter for use in a very high frequency PLL. Referring to FIG. 1, the quasi-digital, high frequency PLL 10 disclosed in the '125 patent includes a phase detector 12, a signed P-to-F converter 14, a 3-phase ring oscillator 16 and a frequency controlled oscillator (FCO) 18. FCO 18 and P-to-F converter 14 allow the use of a clock frequency which is no higher than the generating frequency of the PLL 10 to achieve acceptable phase resolution.
The P-to-F converter 14 converts the phase error information generated by the phase detector 12, which is in the form of UP, DOWN and HOLD signals, to multi-phase analog waveforms (PHASE 1, PHASE 2, PHASE 3) that can be used to drive the FCO 18. The output frequency of the P-to-F converter 14 determines the locking range of the PLL 10. The phase error direction, either plus or minus, is represented by the phase relationship, either leading or lagging, of the multi-phase outputs of the P-to-F converter 14, which the FCO 18 interprets as either an increase, a decrease or no change in the operating frequency.
As shown in FIG. 2, the P-to-F converter 14 disclosed in the '125 patent includes a counting circuit 21 that converts the plus/minus phase error signal UD.sub.-- PI provided by the phase detector 12 to a 7-bit count signal. The three most significant bits (MSB) of the count signal, i.e., the HI.sub.-- CNT signal, are used by a 3-phase waveform generator 25 to generate a 3-phase sawtooth pattern. The four least significant bits (LSB) of the count signal, i.e., the LO.sub.-- CNT signal, are utilized by a pulse density modulation (PDM) circuit 28 to generate a signal that indicates the binary weight of the LSB part of the count. The output of the LSB PDM circuit 28 and the 3-phase sawtooth pattern are applied to three MSB PDM circuits 36, 38, 40. The three carry outputs of the MSB PDM circuits 36, 38, 40 are the digital outputs of the P-to-F converter 14. Following buffering, the three digital outputs of the P-to-F converter 14 are converted to analog signals (PHASE 1, PHASE 2, PHASE 3) by RC filters. The plus/minus phase is indicated by the leading/lagging phase relationship among the output waveforms.
A problem associated with the solution disclosed in the '125 patent is real time delay. That is, since generation of the 3-phase triangular waveform is within the PLL tracking loop, the time required for synthesis directly impacts upon the response time of the phase error correction, which increases the phase jitter of the recovered clock.
U.S. Pat. No. 5,224,125 is hereby incorporated by reference in its entirety.
Commonly-assigned U.S. patent application Ser. No. 08/644,035, filed on May 9, 1996, by Wong Hee and Gabriel Li, now U.S. Pat. No. 5,646,967 provides an improvement over the PLL system disclosed in the '125 patent.
Referring to FIG. 3, U.S. Pat. No. 5,646,967 discloses a triangular waveform synthesizer 100 for a phase-to-frequency converter that generates a multi-phase triangular waveform using both Pulse Density Modulation (PDM) and a DC modulation scheme. The lower counter 102, upper counter 104 and lower PDM circuit 106 are similar to those utilized in the FIG. 2 waveform synthesizer. However, to minimize both delay and logic, while continuing to provide reasonable resolution, a 4-bit upper PDM circuit 112 and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. Since the switching and adding of the DC levels occur in real time, the actual delay for the resultant triangular wave is only that of the 4-bit PDM.
U.S. Pat. No. 5,646,967, is hereby incorporated by reference in its entirety.
The system disclosed in '967 patent improves upon the system disclosed in the '125 patent. Both systems take advantage of Pulse Density Modulation techniques. The key advantage of the system disclosed in the '967 patent over the system disclosed in the '125 patent is its simplicity and short real time delay, which, as stated above, is a major factor in reducing the output jitter of the PLL.
A problem with the system disclosed in the '967 patent, however, is the relatively high energy of the third and higher harmonics of the triangular wave.
Commonly-assigned U.S. patent application Ser. No. 08/644,036, filed May 9, 1996, now U.S. Pat. No. 5,651,036, provides an improvement over both of the above-described systems.
Referring to FIG. 4, U.S. Pat. No. 5,651,036 discloses a phase-to-frequency converter 200 that utilizes a triangular waveform synthesizer to generate a multi-phase triangular waveform using both Pulse Density Modulation (PDM) and a DC modulation scheme. The lower counter 202, upper counter 204, lower PDM circuit 206 and upper PDM circuit 208 are similar to those utilized in the FIG. 3 triangular waveform synthesizer. That is, a PDM and associated logic generates both the multi-phase PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the triangular waveform. However, as shown in FIG. 4, a wave modifier 210 modifies each triangular waveform by reducing the ramp rate at appropriate positions to suppress the third harmonic and its multiples. The ramp rate is proportional to the output of the Pulse Density Modulator. The rate of the PDM output is reduced by gating the output by the wave synthesizer clock signal, thereby reducing the density of the output by one half in the appropriate positions.
U.S. Pat. No. 5,651,036 is hereby incorporated by reference in its entirety.
Although the '036 patent discloses a PLL that substantially improves over the prior art, the response time of the PLL can still be improved.